1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of an interlayer dielectric between and over circuit elements including line elements, such as gate electrodes, polysilicon interconnect lines and the like that create a pronounced surface topography for subsequent manufacturing processes.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein the circuit elements are usually formed in and on a semiconductor layer by performing a plurality of processes, such as lithography processes, etch processes, implantation processes, deposition processes, anneal processes and the like. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost effectiveness. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline silicon or silicon-containing layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors, resistors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the “wiring,” i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of polysilicon lines and the like within the device layer so that a plurality of additional “wiring” layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in very advanced devices, low-k materials having a permittivity of 3.0 or less are used. The metal lines and the surrounding dielectric material will hereinafter be referred to as a metallization layer. Between two adjacent metallization layers and also between the device layer and the first metallization layer, respective interlayer dielectrics are formed through which metal-filled openings are formed to establish the electrical connection between metal lines or between circuit elements and metal lines.
In typical applications, the interlayer dielectric separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates. Upon further device scaling resulting in gate lengths of MOS transistors on the order of less than 50 nm also the lateral dimensions of the metal lines and the vias have to be adapted to the reduced critical dimensions in the device layer. For example, the contact elements formed in the interlayer dielectric separating the device layer from the first metallization layer may have to be formed with dimensions of less than 100 nm. On the other hand, a pronounced surface topography may have been created during the preceding fabrication of the circuit elements, such as the gate electrode structures, which may extend from the basic semiconductor layer with a height of approximately 100 nm and more, even for advanced transistors of the 60 nm technology. Hence, the interlayer dielectric material may have to be provided such that the height levels of the gate electrode structures are at least leveled in other device regions while extra height for forming the contacts may also have to be taken into consideration. Moreover, the manufacturing flow for forming the contact elements may also result in a varying amount of material loss of the interlayer dielectric, depending on process fluctuations. For these reasons, the initial thickness of the interlayer dielectric material may have to additionally provide sufficient process margins when implementing a respective manufacturing flow in a volume production environment. On the other hand, the aspect ratio for patterning and refilling the contact openings may be restricted by technological constraints so that, for given critical dimensions of the contact elements, the thickness of the interlayer dielectric material may not be arbitrarily set to a target height that would accommodate all the process tolerances of the manufacturing processes involved, as will be explained in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a top view of a portion of a semiconductor device 100. The semiconductor device 100 comprises a substrate (not shown in FIG. 1a) above which is formed a semiconductor layer (not shown) in and above which circuit elements, such as a transistor and the like, are formed. For convenience, a circuit element in the form of a transistor 150 is illustrated. The transistor 150 may comprise a gate electrode structure 151, sidewalls of which may be covered by a spacer element 152. Laterally adjacent to the gate electrode structure 151, drain and source regions 153 are provided which, in addition to a channel region (not shown), may be located below the gate electrode structure 151 and may represent an active region in the corresponding semiconductor layer. The active region may be bordered by an isolation structure 102, above which also a portion of the gate electrode structure 151 may be positioned, thereby defining a contact region 154 that is in contact with a contact plug or contact element 1 10. Similarly, one or more contact elements 111 may be provided so as to connect to the drain and/or source regions 153, wherein, for convenience, only one such contact element 111 is illustrated. It should be appreciated that the contact elements 110, 111 are typically formed in an appropriate interlayer dielectric material which for convenience is not shown in FIG. 1a. 
FIG. 1b schematically illustrates a cross-sectional view along the line 1b as shown in FIG. 1a, wherein the semiconductor device 100 is illustrated in a manufacturing stage in which the contact elements 110, 111 are not yet formed. As shown, the semiconductor device 100 comprises a substrate 101, which represents any appropriate carrier material, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. A silicon-based semiconductor layer 103 is formed above the substrate 101, and the isolation structure 102, for instance in the form of a trench isolation, defines an active region 104 in which are positioned the drain and source regions 153, i.e., respective dopant concentrations, so as to define respective PN junctions with the remaining portion of the active region 104. Furthermore, a gate insulation layer 156 is formed on the semiconductor material of the active region 104, thereby isolating the gate electrode structure 151 from the active region 104. Moreover, metal silicide regions 155 may be formed in the drain and source regions 153, thereby defining a contact region thereof. Similarly, the metal silicide 155 may also be formed on the gate electrode structure 151 including the contact portion 154 (FIG. 1a), thereby also defining a respective contact region for the gate electrode structure 151. Furthermore, the semiconductor device comprises an interlayer dielectric material 105 which typically comprises two or more dielectric layers, such as the layers 105A and 105B, wherein the former one may represent a contact etch stop layer comprised of silicon nitride and the latter one may represent a silicon dioxide material.
In advanced applications, the etch stop layer 105A may additionally act as a strain-inducing material for generating a desired type of strain in the active region 104. Therefore, the layer 105A may be formed so as to have a high internal stress level, while the thickness thereof is selected such that a high mount of stressed material may be positioned in the vicinity of the transistor 150. However, the thickness of the layer 105A is restricted by the gap fill capabilities of plasma enhanced deposition techniques for forming the highly stressed silicon nitride material that is usually employed for the layer 105A. For example, the thickness of the layer 105A may be restricted to less than approximately 100 nm in sophisticated devices. Furthermore, the thickness of the interlayer dielectric material 105 is selected so as to obtain a desired height level above the active region 104 and the isolation structure 102 and to provide a sufficient distance between the gate electrode structure 151 and a first metallization layer still to be formed, while also taking into consideration a material loss during the further manufacturing flow for forming the contact elements 110, 111 (FIG. 1a) and the first metallization layer. On the other hand, the thickness of material 105 and thus of the layer 105B may not exceed a certain limit in order to respect the aspect ratio restrictions for patterning and filling the contact elements 110, 111.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1b may comprise the following processes. After forming the circuit element 150 on the basis of well-established techniques in accordance with design rules of the respective technology node, which includes forming the appropriate gate insulation layer 156 and patterning the same along with the gate electrode structure 151 by sophisticated lithography and etch techniques. The drain and source regions 153 may be formed by ion implantation, using the spacer structure 152 as an appropriate implantation mask. After any anneal cycles, the metal silicide regions 155 are formed, followed by the deposition of the etch stop layer 105A, typically by PECVD, since PECVD of silicon nitride may be accomplished at moderately low temperatures of less than approximately 600° C., which is compatible with preceding manufacturing processes and materials, such as metal silicides 155 and the like. As previously discussed, the ongoing shrinkage of feature sizes also entails that a distance between neighboring circuit elements in densely packed device regions is reduced and may be less than approximately 150 nm in currently manufactured CPUs of the 65 nm technology node. Hence, any deposition techniques for forming a dielectric layer for embedding the gate electrode structure 151, which may have a height of approximately 100-150 nm, have to meet the requirements of an appropriate fill capability so as to reliably and completely fill the empty spaces between the neighboring circuit elements. Moreover, the process parameters of the PECVD process for the deposition of the silicon nitride material of the layer 105A in a highly stressed state may be selected so as to obtain the desired stress level rather than obtaining an optimum fill behavior. Therefore, for well-established PECVD process recipes for silicon nitride, the layer 105A may be deposited in a more or less conformal fashion only with a thickness of approximately 100 nm or less.
Thereafter, the silicon dioxide layer 105B is deposited, which is typically done by PECVD on the basis of precursors TEOS (tetra-ethyl-ortho-silicate) and oxygen, since PECVD allows the deposition of silicon dioxide in a moderately conformal manner—yet with less gap filling qualities compared to thermal CVD—with relatively high mechanical stability at temperatures below 600° C. at high deposition rates, which provides a high production yield. After deposition, the silicon dioxide layer 105B has a certain topography caused by the underlying structure of the gate electrode structure 151, which may jeopardize subsequent manufacturing processes, such as a photolithography step for forming contact openings for the contact elements 110, 111. Consequently, the standard process flow requires that the silicon dioxide layer 105B be planarized, typically by chemical mechanical polishing (CMP), wherein excess material of the silicon dioxide layer 105B is removed by chemical and mechanical interaction with a slurry and a polishing pad to finally obtain a substantially planarized surface 105S of the silicon dioxide layer 105B. The CMP process itself is a highly complex process and requires sophisticated process recipes, wherein the removal rate significantly depends on the characteristics of the silicon dioxide layer 105B, such as density, mechanical stress, water contents and the like. Due to the complexity of the CMP process and due to any fluctuations in the preceding processes, such as the deposition of the layer 105B, the finally obtained height 105H of the layer 105B above the gate electrode structure 151 may also vary during volume production processes. Moreover, the height 105H may have to also accommodate further material losses in subsequent processes, while, on the other hand, a critical height above the active region should not be exceeded, since here the high aspect ratio contact elements 111 are to be formed so that extra height in this area may increase the probability of creating contact failures.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, the contact elements 110 (not shown in this cross-sectional view) and 111 are formed in the interlayer dielectric material 105 and typically comprise a barrier material 111A, for instance in the form of a titanium liner and a titanium nitride liner, while the actual fill material 111B may be provided in the form of a tungsten material.
The contact elements 110, 111 may be formed by well-established techniques including deposition processes for forming an anti-reflective coating (ARC) material and patterning the same by photolithography to obtain an etch mask for forming contact openings in the layers 105B and 105A. Thereafter, the etch mask is removed and the barrier material 111A and the fill material 111B are deposited. During the preceding sequence, that is, the patterning of the contact openings and the filling thereof, the process yield may depend on the aspect ratio of the contact openings, as previously explained. Next, excess material of the fill material 111B is removed, for instance by CMP. However, during the patterning of the contact openings and the removal of the excess material, a further material loss of the layer 105B may occur, as indicated by 105L. This additional reduction in height 105L may be approximately 100 nm and may need to be taken into consideration when selecting the initial target height of the layer 105, thereby further contributing to an increased aspect ratio of the contact element 111 and at a lesser extent of the contact element 110.
Consequently, the contact element 111 connecting to the drain or source region 153 may have a moderately high aspect ratio, since the lateral size thereof is substantially restricted by the lateral dimension of the drain and source regions 153, while the depth of the contact element 111 is determined by the thickness of the interlayer dielectric material 105. On the other hand, the contact element 110 only has to extend down to the top surface of the gate electrode structure 151, i.e., to the contact portion 154 (FIG. 1a), while also the lateral dimension of the contact element 110 may be different compared to the element 111, depending on the size and shape of the contact portion 154. The contact elements 110, 111 typically comprise a barrier material in the form of a titanium liner, followed by a titanium nitride liner, while the actual fill material may be provided in the form of a tungsten material.
FIG. 1d schematically illustrates the device 100 with a metallization layer formed above the interlayer dielectric material 105. The metallization layer, which is the first metallization layer of the device 100, typically comprises an etch stop layer 123, for instance in the form of silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like, on which may be formed an appropriate dielectric material 124, such as a low-k dielectric material having a relative permittivity of 3.0 or less. Moreover, respective metal lines 121, 122 are formed in the dielectric material 124 and connect to the contact elements 110, 111, respectively. The metal lines 121, 122 may comprise a copper-containing metal in combination with an appropriate barrier material, such as a material comprising tantalum, tantalum nitride and the like. Finally, a cap layer 126 is typically provided to confine the copper material in the metal lines 121, 122, which may be accomplished on the basis of dielectric materials such as silicon nitride, silicon carbide and the like.
The metallization layer may be formed by depositing the etch stop layer 123 followed by the deposition of the dielectric material 124. Next, respective trenches are formed in the dielectric material 124 according to well-established single damascene strategies. Next, the metal lines 121, 122 may be formed by depositing a barrier layer and filling in a copper-based material, for instance on the basis of electroplating, which may be preceded by the deposition of a copper seed layer. Finally, any excess material may be removed, for instance by CMP, and the cap layer 126 may be deposited. During the patterning of the trenches, the reduced height 105R may need to be within specified tolerances so as to ensure a reliable patterning process. However, due to the preceding process fluctuations, in particular the CMP processes for planarizing the layer 105B, in combination with the material loss 105L and the stringent requirements with respect to the aspect ratio of the contact elements 110, 111, the required minimum height 105R may be difficult to be achieved in sophisticated applications, such as the formation of devices of the 65 nm or 45 nm technology.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.